74HC109 Dual J-K Negative-Edge-Triggered Flip-Flops IC (74109) DIP-16 Package

74HC109 Dual J-K Positive-Edge-Triggered Flip-Flop IC – DIP-16 Package The 74HC109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product is known as 74109 IC, 74109 SMD IC, 74HC109 IC, 74HC109 SMD IC, Components, Dual J-K Positive-Edge-Triggered Flip-Flops IC, Dual J-K Positive-Edge-Triggered Flip-Flops SMD IC, SN74HC109D, CD74HC109M, 74HC109D, CD74HC109E, SN74HC109N, CD74HC109ME4. Features :- Input Levels : – For 74HC109: CMOS level – For 74HCT109: TTL level J and K inputs for easy D-type flip-flop Toggle flip-flop or “do nothing” mode Specified in compliance with JEDEC standard no. 7A ESD protection: – HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V Multiple package options Specifications :- Symbol Parameter Min Max Unit VCC Supply Voltage 2.0 6.0 V IIK Input Clamping Current ±20 mA IOK Output Clamping Current ±20 mA IOK Output Current ±25 mA ICC Supply Current 50 mA IGND Ground Current -50 mA Tstg Storage Temperature -65 150 °C Ptot Total Power Dissipation 500 mW Package Includes :- 1 X 74HC109 Dual J-K Negative-Edge-Triggered Flip-Flops IC (74109) DIP-16 Package