74HC161 4-Bit Presettable Synchronous Binary Counter IC (74161) DIP-16 Package

The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters maybe preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time ,according to the following formula: Features :- Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Asynchronous reset Output capability: standard ICC category: MSI Parameter Condition Typical Unit HC HCT Propagation delay (tPHL) CL = 15 pF; VCC = 5 V 54 64 ns CP to Qn 23 43 ns CP to TC 28 48 ns MR to Qn 29 46 ns MR to TC 30 51 ns CET to TC 17 35 ns set-up time CEP, CET to CP 170 47 output transition time 7 15 ns clock pulse width HIGH or LOW 16 7 ns CET to TC 17 35 ns master reset pulse width; LOW 20 10 MHz removal time MR to CP 20 6 pF maximum clock pulse frequency 4.6 13 pF Package Includes :- 1 X 74HC161 4-Bit Presettable synchronous Binary counter IC (74161) DIP-16 Package