74HC4024 7-Stage Binary Ripple Counter IC (744024 IC) DIP-14 Package

The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Applications :- Frequency dividing circuits Time delay circuits Features :- Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 ℃ to +80 ℃ and from -40 ℃ to +125 ℃ Specifications :- Symbol Parameter Min Max Unit VCC Supply Voltage -0.5 +7 V IIK input clamping current - +20 mA Iok output clamping current - +20 mA IO output current - +25 mA ICC supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW Package Includes :- 1 X 74HC4024 7-Stage Binary Ripple Counter IC (744024 IC) DIP-14 Package